The present disclosure relates to a transmission circuit in a data interface having two or more lanes and a communication system.
A transmission circuit having two or more lanes (or channels) is mainly based on a common divider scheme or an individual divider scheme.
Referring to FIG. 1, there is shown an exemplary configuration of a communication apparatus having a transmission circuit based on a common divider scheme.
A communication 1 in FIG. 1 has a logic layer block 2 and a transmission circuit 3.
The logic layer block 2 supplies 10-bit data Pdata [9:0] of two or more (four in this example) lanes (or channels) to the transmission circuit 3.
The transmission circuit 3 has four lane blocks 31-0 through 31-3, a PLL circuit 32, and a divider (DIV) 33 connected commonly to the four lane blocks 31-0 through 31-3.
The four lane blocks 31-0 through 31-3, a PLL circuit 32 each have a same configuration.
The PLL circuit 32 generates a drive clock PLLCLK synchronized with a reference clock REFCLK and supplies the drive clock PLLCLK to the divider 33 and the lane blocks 31-0 through 31-3.
The divider 33 divides the drive clock PLLCLK to generate a load signal LOAD and a division clock CLK10, and supplies the load signal LOAD and the divide clock CLK10 to the lane blocks 31-0 through 31-3.
It should be noted that the divider 33 is reset by a reset signal RSTX.
The divide clock CLK10 of the divider 33 is used also as a system clock of the logic layer block 2.
The lane blocks 31-0 through 31-3 have 10:1 parallel-to-serial converters) P/S0 through P/S3 and differential output blocks DF0 through DF3, respectively.
Referring to FIG. 2, there is shown an exemplary configuration of the parallel-to-serial converter.
Referring to FIG. 3, there is shown a timing chart of the parallel-to-serial converter shown in FIG. 2.
The parallel-to-serial converter P/S (0 through 3) shown in FIG. 2 is formed by flip-flops FF0 through FF9 and FF10 and selector SL0 through SL9.
The parallel-to-serial converter P/S has the FF10 at the data input stage. The flip-flop FF10 receives parallel data Pdata at data input D from the logical layer block 2, latches the received data Pdata in synchronization with divide clock CLK10 from the divider 33, and outputs the latched data.
The data output Q of the flip-flop FF-10 is connected to the first input terminal of the selectors SL9 through SL0. The selectors SL9 through SL0 select the first input terminal, namely, the output data of the flip-flop FF10 when a load signal LOAD from the divider 33 is at the high level and select the input data of the second input terminal when the load signal LOAD is at the low level.
The flop-flops FF9 through FF0 are connected in a cascaded manner, a drive clock PLLCLK being supplied to the clock input from the PLL circuit 32.
The data input D of the flip-flop FF9 is connected to the output terminal of the selector SL9, and the second input terminal of the selector SL9 is fixed to the low level.
The data input D of the flip-flop FF8 is connected to the output terminal of the selector SL8, and the second input terminal of the selector SL8 is connected to the data output Q of the flip-flip FF9.
The data input D of the flip-flop FF7 is connected to the output terminal of the selector SL7, and the second input terminal of the selector SL7 is connected to the data output Q of the flip-flip FF8.
The data input D of the flip-flop FF6 is connected to the output terminal of the selector SL6, and the second input terminal of the selector SL6 is connected to the data output Q of the flip-flip FF7.
The data input D of the flip-flop FF5 is connected to the output terminal of the selector SL5, and the second input terminal of the selector SL5 is connected to the data output Q of the flip-flip FF6.
The data input D of the flip-flop FF4 is connected to the output terminal of the selector SL4, and the second input terminal of the selector SL4 is connected to the data output Q of the flip-flip FF5.
The data input D of the flip-flop FF3 is connected to the output terminal of the selector SL3, and the second input terminal of the selector SL3 is connected to the data output Q of the flip-flip FF4.
The data input D of the flip-flop FF2 is connected to the output terminal of the selector SL2, and the second input terminal of the selector SL2 is connected to the data output Q of the flip-flip FF3.
The data input D of the flip-flop FF1 is connected to the output terminal of the selector SL1, and the second input terminal of the selector SL1 is connected to the data output Q of the flip-flip FF2.
The data input D of the flip-flop FF0 is connected to the output terminal of the selector SL0, and the second input terminal of the selector SL0 is connected to the data output Q of the flip-flip FF1.
The data output Q of the flip-flop FF0 is connected to the input terminal of the differential output block DF.
In the parallel-to-serial converter P/S, the data Pdata of the corresponding lane is latched in synchronization with the divide clock CLK10 from the divider 33, a resultant latched data PDATALT being outputted to the first input terminals of the selectors SL9 through SL0.
Next, while the load signal LOAD is at the high level, the data PDATALT is latched by the flip-flops FF0 through FF0 in synchronization with the drive clock PLLCLK.
The latched data of the flip-flops FF9 through FF0 is shifted in synchronization with the drive clock PLLCLK after the changing of the load signal LOAD from the high level to the low level, the shifted data being outputted from the differential output block DF as differential serial data TX.
Referring to FIG. 4, there is shown an exemplary configuration of the communication apparatus having a transmission circuit based on an individual divider scheme.
In a communication apparatus 1A shown in FIG. 4, dividers 33-0 through 33-3 are arranged for lane blocks 31A-1 through 31A-3, respectively, of an transmission circuit 3A.
In addition, FIFO 4-1 through FIFO 4-3 are inserted between the data output of a logic layer block 2 and the input blocks of the lane blocks 31A-1 through 31A-3 of the transmission circuit 3A.